As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate back end of the line (BEOL) and middle of the line (MOL) metallization features, e.g., interconnects, due to the critical dimension (CD) scaling and process capabilities, as well as the materials that are used to fabricate such structures.
For example, to manufacture interconnect structures for active gate contacts and source/drain contacts, it is necessary to remove dielectric material above and adjacent to the gate structures. The removal of the dielectric material is provided by an etching process which also tends to erode the spacer material of the gate structure. That is, the low-k dielectric material used for the spacer or sidewalls of the gate structure can be eroded away in the downstream etching processes used to form the openings for the contacts. This loss of sidewall material will expose the metal material of the gate structure, resulting in a short between the metal material of the gate structure and the metal material used to form the contact, itself.